Decoder

Flow of Data in player:

[Notes from Hitachi presentation]

Stage 1: SYNC detection, 8/16 Demodulation, ID Detection.

A total of 8 sync codes are inserted into the 8/16 modulated channel bitstream representing the current physical sector. Sync code words are unique in the 8/16 code table (so they cannot be generated by the 8-to-16 mapping).

The Detection stage looks for sync codes in order to determine where sectors begin and end. Here the channel bit rate input to this block is 26.16 Mbits/sec, and output is 13 Mbit/sec.

Stage 2: Error detection and correction

If the check bits (EDC) don't match the fingerprint of the unscrambled data, the Reed Soloman bytes (IEC) are used to attempt error correction of the corrupted data. Here the channel rate output by this block is 11.08 Mbit/sec (~2 Mbit/sec of error correction parity data, IEC, has been stripped).

Stage 3: Descramble/Decrypt

Data on the disc is descrambled for purposes of further DC energy reduction. Decryption is performed for purposes of copy protection.

Stage 4: EDC Check

The fingerprint of the unscrambled data is checked against the EDC code to verify whether the data was correctly descrambled.

Stage 5: Track buffer

This FIFO (First In First Out buffer) maps the constant user data bit rate of 11.08 Mbit/sec to the variable bit rate of the program streams. DSI and PCI packets (used to control the behavior of the player) are stripped yielding a 10.08 mbit/sec rate into the MPEG systems decoder. The mux_rate of all program streams is 10.08 mbit/sec regardless of actual elementary stream rates.

Stage 6: Transfer to MPEG system decoder.

Packets are demultiplexed in the system decoder, and distributed to the respective elementary stream decoders (video, audio, subpicture, VBI).